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PCF8562
Universal LCD driver for low multiplex rates
Rev. 04 -- 18 March 2009 Product data sheet
1. General description
The PCF8562 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 32 segments. The PCF8562 is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). AEC-Q100 compliant (PCF8562TT/S400) for automotive applications.
2. Features
I I I I I Single chip LCD controller and driver Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing Selectable display bias configuration: static, 12 or 13 Internal LCD bias generation with voltage-follower buffers 32 segment drives: N Up to sixteen 7-segment numeric characters N Up to eight 14-segment alphanumeric characters N Any graphics of up to 128 elements 32 x 4-bit RAM for display data storage Auto-incremented display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5 V Wide logic LCD supply range: N From 2.5 V for low-threshold LCDs N Up to 6.5 V for guest-host LCDs and high-threshold twisted nematic LCDs Low power consumption 400 kHz I2C-bus interface No external components Manufactured in silicon gate CMOS process
I I I I I I I
I I I I
NXP Semiconductors
PCF8562
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1. Ordering information Package Name PCF8562TT/2 PCF8562TT/S400/2 Description Version TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1 body width 6.1 mm TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1 body width 6.1 mm Type number
4. Marking
Table 2. Marking codes Marking code PCF8562TT PCF8562TT Type number PCF8562TT/2 PCF8562TT/S400/2
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PCF8562
Universal LCD driver for low multiplex rates
5. Block diagram
BP0 BP2 BP1 BP3 22 VLCD 21 23 24 25 S0 to S31 26 to 48, 1 to 9 DISPLAY SEGMENT OUTPUTS
BACKPLANE OUTPUTS
LCD VOLTAGE SELECTOR DISPLAY CONTROLLER
DISPLAY REGISTER
VSS
20
LCD BIAS GENERATOR
OUTPUT BANK SELECT AND BLINK CONTROL
CLK SYNC
13 CLOCK SELECT 12 AND TIMING BLINKER TIMEBASE
PCF8562
DISPLAY RAM 40 x 4-BIT
OSC VDD SCL SDA
15 14 11 10
OSCILLATOR
POWER-ON RESET
COMMAND DECODER
WRITE DATA CONTROL
DATA POINTER AND AUTO INCREMENT
INPUT FILTERS
I2C-BUS CONTROLLER 19 SA0
SUBADDRESS COUNTER 16 A0 A1 17 A2
001aac262
18
Fig 1.
Block diagram of PCF8562
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PCF8562
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
S23 S24 S25 S26 S27 S28 S29 S30 S31
1 2 3 4 5 6 7 8 9
48 S22 47 S21 46 S20 45 S19 44 S18 43 S17 42 S16 41 S15 40 S14 39 S13 38 S12 37 S11 36 S10 35 S9 34 S8 33 S7 32 S6 31 S5 30 S4 29 S3 28 S2 27 S1 26 S0 25 BP3
001aac263
SDA 10 SCL 11 SYNC 12 CLK 13 VDD 14 OSC 15 A0 16 A1 17 A2 18 SA0 19 VSS 20 VLCD 21 BP0 22 BP2 23 BP1 24
PCF8562TT
Top view. For mechanical details, see Figure 20.
Fig 2.
Pinning diagram for PCF8562
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PCF8562
Universal LCD driver for low multiplex rates
6.2 Pin description
Table 3. Symbol SDA SCL SYNC CLK VDD OSC A0 to A2 SA0 VSS VLCD BP0 to BP3 S0 to S22, S23 to S31 Pin description Pin 10 11 12 13 14 15 16 to 18 19 20 21 22 to 25 26 to 48, 1 to 9 Description I2C-bus serial data input and output I2C-bus serial clock input cascade synchronization input or output external clock input or output supply voltage internal oscillator enable input subaddress inputs I2C-bus address input; bit 0 ground supply voltage LCD supply voltage LCD backplane outputs LCD segment outputs
7. Functional description
The PCF8562 is a versatile peripheral device designed to interface any microprocessor or microcontroller with a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 32 segments. The possible display configurations of the PCF8562 depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 4. All of these configurations can be implemented in the typical system shown in Figure 3.
Table 4. Display configurations 7-segment numeric 14-segment numeric Characters Indicator symbols 8 6 4 2 16 12 8 4 128 dots (4 x 32) 96 dots (3 x 32) 64 dots (2 x 32) 32 dots (1 x 32) Dot matrix
Number of:
Backplanes Segments Digits Indicator symbols 4 3 2 1 128 96 64 32 16 12 8 4 16 12 8 4
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PCF8562
Universal LCD driver for low multiplex rates
VDD R
tr 2Cb SDA 10 SCL OSC 11 15 16 A0
VDD 14
VLCD 21
32 segment drives
LCD PANEL
HOST MICROPROCESSOR/ MICROCONTROLLER
PCF8562
4 backplanes
17 A1 18 A2 19 20
(up to 128 elements)
SA0 VSS
001aac264
VSS
The resistance of the power lines must be kept to a minimum.
Fig 3.
Typical system configuration
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCF8562. The internal oscillator is enabled by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application.
7.1 Power-on reset
At power-on the PCF8562 resets to the following starting conditions:
* * * * * * * *
All backplane outputs are set to VLCD All segment outputs are set to VLCD The selected drive mode is: 1:4 multiplex with 13 bias Blinking is switched off Input and output bank selectors are reset The I2C-bus interface is initialized The data pointer and the subaddress counter are cleared (set to logic 0) Display is disabled
Data transfers on the I2C-bus must be avoided for 1 ms following power-on to allow the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between VLCD and VSS. The middle resistor can be bypassed to provide a 12 bias voltage level for the 1:2 multiplex configuration. The LCD voltage can be temperature compensated externally using the supply to pin VLCD.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command (see Section 7.17) from the command decoder. The biasing
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PCF8562
Universal LCD driver for low multiplex rates
configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in Table 5.
Table 5. LCD drive mode static 1:2 multiplex 1:2 multiplex 1:3 multiplex 1:4 multiplex Discrimination ratios Number of: LCD bias Backplanes Levels configuration 1 2 2 3 4 2 3 4 4 4 static
1 2 1 3 1 3 1 3
V off ( RMS ) -------------------------V LCD
0 0.354 0.333 0.333 0.333
V on ( RMS ) V on ( RMS ) ------------------------ D = -------------------------V off ( RMS ) V LCD
1 0.791 0.745 0.638 0.577 2.236 2.236 1.915 1.732
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth. Multiplex drive modes of 1:3 and 1:4 with 12 bias are possible but the discrimination and hence the contrast ratios are smaller.
1 Bias is calculated by ------------ , where the values for a are 1+a
a = 1 for 12 bias a = 2 for 13 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation
2 1 1 -- + ( n - 1 ) x ------------ - 1 + a n ----------------------------------------------------------n
V on ( RMS ) =
V LCD
(1)
where VLCD is the resultant voltage at the LCD segment and where the values for n are n = 1 for static mode n = 2 for 1:2 multiplex n = 3 for 1:3 multiplex n = 4 for 1:4 multiplex The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with the equation: V off ( RMS ) =
V LCD
a - ( 2a + n ) -------------------------------2 n x (1 + a)
2
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from the equation:
V on ( RMS ) ----------------------- = V off ( RMS )
(a + 1) + (n - 1) ------------------------------------------2 (a - 1) + (n - 1)
2
(3)
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PCF8562
Universal LCD driver for low multiplex rates
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1 1 2 bias 2 bias
is
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
21 is ---------- = 1.528 . 3
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows:
* 1:3 multiplex (12 bias):V LCD =
6 x V off ( RMS ) = 2.449V off ( RMS )
) * 1:4 multiplex (12 bias): V LCD = ( 4 x 3 - = 2.309V off ( RMS ) ---------------------
3
These compare with V LCD = 3V off ( RMS ) when 13 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage.
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PCF8562
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Figure 4.
Tfr VLCD BP0 VSS VLCD Sn VSS VLCD state 1 (on) state 2 (off) LCD segments
Sn+1
VSS (a) Waveforms at driver. VLCD
state 1
0V
-VLCD VLCD
state 2
0V
-VLCD (b) Resultant waveforms at LCD segment.
mgl745
(1) Vstate1(t) = VSn(t) - VBP0(t). (2) Von(RMS) = VLCD. (3) Vstate2(t) = VSn+1(t) - VBP0(t). (4) Voff(RMS) = 0 V.
Fig 4.
Static drive mode waveforms
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PCF8562
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD bias voltages of 12 bias or 13 bias as shown in Figure 5 and Figure 6.
Tfr VLCD BP0 VLCD / 2 VSS state 1 VLCD BP1 VLCD / 2 VSS VLCD Sn VSS VLCD state 2 LCD segments
Sn+1
VSS (a) Waveforms at driver. VLCD VLCD / 2 state 1 0V -VLCD / 2 -VLCD VLCD VLCD / 2 state 2 0V -VLCD / 2 -VLCD (b) Resultant waveforms at LCD segment.
mgl746
(1) Vstate1(t) = VSn(t) - VBP0(t). (2) Von(RMS) = 0.791VLCD. (3) Vstate2(t) = VSn+1(t) - VBP1(t). (4) Voff(RMS) = 0.354VLCD.
Fig 5.
Waveforms for the 1:2 multiplex drive mode with 12 bias
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PCF8562
Universal LCD driver for low multiplex rates
Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD (b) Resultant waveforms at LCD segment.
mgl747
LCD segments
state 1 state 2
Sn+1
(1) Vstate1(t) = VSn(t) - VBP0(t). (2) Von(RMS) = 0.745VLCD. (3) Vstate2(t) = VSn+1(t) - VBP1(t). (4) Voff(RMS) = 0.333VLCD.
Fig 6.
Waveforms for the 1:2 multiplex drive mode with 13 bias
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PCF8562
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies (see Figure 7).
Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD Sn+2 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD state 1 state 2 LCD segments
BP1
BP2
(b) Resultant waveforms at LCD segment.
mgl748
(1) Vstate1(t) = VSn(t) - VBP0(t). (2) Von(RMS) = 0.638VLCD. (3) Vstate2(t) = VSn+1(t) - VBP1(t). (4) Voff(RMS) = 0.333VLCD.
Fig 7.
Waveforms for the 1:3 multiplex drive mode with 13 bias
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PCF8562
Universal LCD driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see Figure 8).
Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD state 1 state 2 LCD segments
BP1
BP3
Sn
Sn+1
Sn+2
2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3
Sn+3
state 1
0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3
state 2
0V -VLCD / 3 -2VLCD / 3 -VLCD
(b) Resultant waveforms at LCD segment.
mgl749
(1) Vstate1(t) = VSn(t) - VBP0(t). (2) Von(RMS) = 0.577VLCD. (3) Vstate2(t) = VSn+1(t) - VBP1(t). (4) Voff(RMS) = 0.333VLCD.
Fig 8.
Waveforms for the 1:4 multiplex drive mode with 13 bias
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PCF8562
Universal LCD driver for low multiplex rates
7.5 Oscillator
7.5.1 Internal clock
The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC to pin VSS. After power-on, pin SDA must be HIGH to guarantee that the clock starts.
7.5.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD frame signal frequency is determined by the clock frequency (fclk). A clock signal must always be supplied to the device; removing the clock freezes the LCD in a DC state.
7.6 Timing
The PCF8562 timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency is a fixed division of the clock frequency from either f clk the internal or an external clock: f fr = ------- . 24
7.7 Display register
The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and each column of the display RAM.
7.8 Segment outputs
The LCD drive section includes 32 segment outputs S0 to S31 which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display latch. When less than 32 segment outputs are required, the unused segment outputs should be left open-circuit.
7.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required, the unused outputs can be left open-circuit. In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements.
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Universal LCD driver for low multiplex rates
7.10 Display RAM
The display RAM is a static 32 x 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The display RAM bit map Figure 9 shows the rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and the columns 0 to 31 which correspond with the segment outputs S0 to S31. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2 and BP3 respectively.
display RAM addresses (rows) / segment outputs (S) 0 0 display RAM bits 1 (columns) / backplane outputs 2 (BP) 3
001aac265
1
2
3
4
27
28
29
30
31
Display RAM bit map showing direct relationship between RAM addresses and segment outputs; also between bits in a RAM word and the backplane outputs.
Fig 9.
Display RAM bit map
When display data is transmitted to the PCF8562, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Figure 10; the RAM filling organization depicted applies equally to other LCD types. The following applies to Figure 10:
* In the static drive mode, the eight transmitted data bits are placed in row 0 of eight
successive 4-bit RAM words.
* In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into
row 0 and 1 of four successive 4-bit RAM words.
* In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1 and 2 to
three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted.
* In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into
row 0, 1, 2 and 3 of two successive 4-bit RAM words.
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Product data sheet Rev. 04 -- 18 March 2009
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drive mode
LCD segments
LCD backplanes
display RAM filling order display RAM addresses (columns)/segment outputs (S) byte1
transmitted display byte
Sn+2 Sn+3 static Sn+4 Sn+5 Sn+6
e d f
a b g c
Sn+1 Sn Sn+7 DP
BP0 display RAM bits (rows)/ backplane outputs (BP) 0 1 2 3
n c x x x
n+1 b x x x
n+2 a x x x
n+3 f x x x
n+4 g x x x
n+5 e x x x
n+6 d x x x
n+7 DP x x x MSB cba f LSB g e d DP
BP0 Sn 1:2 Sn+1
f g a b
display RAM addresses (columns)/segment outputs (S) byte1 byte2 n display RAM bits (rows)/ backplane outputs (BP) 0 1 2 3 a b x x n+1 f g x x n+2 e c x x n+3 d DP x x MSB ab f LSB g e c d DP
multiplex Sn+2 Sn+3
e d c
BP1 DP
Sn+1 1:3 Sn+2
f
a b g
BP0 Sn display RAM bits (rows)/ backplane outputs (BP)
display RAM addresses (columns)/segment outputs (S) byte1 byte2 byte3 n 0b 1 DP 2c 3x n+1 a d g x n+2 f e x x MSB b DP c a d g f LSB
multiplex
e d c
Universal LCD driver for low multiplex rates
BP1 DP
BP2
e
display RAM addresses (columns)/segment outputs (S) byte1 byte2 byte3 byte4 byte5 Sn 1:4
f g a b
BP0
BP2 display RAM bits (rows)/ backplane outputs (BP)
n 0a 1c 2b 3 DP
n+1 f e g d MSB a c b DP f LSB egd
multiplex
e c d
BP1 DP
BP3
Sn+1
PCF8562
001aaj646
x = data bit unchanged.
Fig 10. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus
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PCF8562
Universal LCD driver for low multiplex rates
7.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see Section 7.17). Following this command, an arriving data byte is stored at the display RAM address indicated by the data pointer. The filling order shown in Figure 10. After each byte is stored, the contents of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode:
* * * *
In static drive mode by eight In 1:2 multiplex drive mode by four In 1:3 multiplex drive mode by three In 1:4 multiplex drive mode by two
If an I2C-bus data access is terminated early then the state of the data pointer is unknown. The data pointer should be re-written prior to further RAM accesses.
7.12 Subaddress counter
The storage of display data is determined by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the device-select command (see Section 7.17). If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The hardware subaddress must not be changed while the device is being accessed on the I2C-bus interface.
7.13 Output bank selector
The output bank selector selects one of the four rows per display RAM address for transfer to the display register. The actual row selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence.
* In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, row 2 and then row 3.
* In 1:3 multiplex mode, row 0, 1 and 2 are selected sequentially * In 1:2 multiplex mode, row 0 and 1 are selected * In static mode, row 0 is selected
The PCF8562 includes a RAM bank switching feature in the static and 1:2 drive modes. In the static drive mode, the bank-select command (see Section 7.17) may request the contents of row 2 to be selected for display instead of the contents of row 0. In 1:2 mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled.
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Universal LCD driver for low multiplex rates
7.14 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. The bank-select command (see Section 7.17) can be used to load display data in row 2 in static drive mode or in rows 2 and 3 in 1:2 mode. The input bank selector functions are independent of the output bank selector.
7.15 Blinker
The PCF8562 has a very versatile display blinking capability. The whole display can blink at a frequency selected by the blink-select command (see Table 13). Each blink frequency is a fraction of the clock frequency; the ratio between the clock frequency and blink frequency depends on the blink mode selected (see Table 6). An additional feature allows an arbitrary selection of LCD segments to blink in the static and 1:2 drive modes. This is implemented without any communication overheads by the output bank selector which alternates the displayed data between the data in the display RAM bank and the data in an alternative RAM bank at the blink frequency. This mode can also be implemented by the blink-select command (see Section 7.17). In the 1:3 and 1:4 drive modes, where no alternative RAM bank is available, groups of LCD segments can blink selectively by changing the display RAM data at fixed time intervals. The entire display can blink at a frequency other than the nominal blink frequency by sequentially resetting and setting the display enable bit E at the required rate using the mode-set command (see Section 7.17).
Table 6. off 1 Blinking frequencies[1] Normal operating mode ratio Nominal blink frequency blinking off 2 Hz
Blink mode
f clk --------768 f clk -----------1536 f clk -----------3072
2
1 Hz
3
0.5 Hz
[1]
Blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz correspond to an oscillator frequency (fclk) of 1536 Hz (see Section 11).
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Universal LCD driver for low multiplex rates
7.16 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
7.16.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 11).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 11. Bit transfer
7.16.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P (see Figure 12).
SDA
SDA
SCL S START condition P STOP condition
SCL
mbc622
Fig 12. Definition of START and STOP conditions
7.16.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Figure 13).
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MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
mga807
Fig 13. System configuration
7.16.4 Acknowledge
The number of data bytes that can be transferred from transmitter to receiver between the START and STOP conditions is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal on the bus that is asserted by the transmitter during which time the master generates an extra acknowledge related clock pulse. An addressed slave receiver must generate an acknowledge after receiving each byte. Also a master receiver must generate an acknowledge after receiving each byte that has been clocked out of the slave transmitter. The acknowledging device must pull-down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition (see Figure 14).
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement
mbc602
1
2
8
9
Fig 14. Acknowledgement of the I2C-bus
7.16.5 I2C-bus controller
The PCF8562 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8562 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress.
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7.16.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.
7.16.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8562. The least significant bit of the slave address that a PCF8562 will respond to is defined by the level tied to its SA0 input. The PCF8562 is a write-only device and will not respond to a read access. The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of two possible PCF8562 slave addresses available. All PCF8562s whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is ignored by all PCF8562s whose SA0 inputs are set to the alternative level.
R/W slave address S
acknowledge by all addressed PCF8576Ds
acknowledge by A0, A1 and A2 selected PCF8576D only
S 011100A0AC
0 1 byte
COMMAND
A
DISPLAY DATA
A
P
n 1 byte(s)
n 0 byte(s) update data pointers and if necessary, subaddress counter
mdb078
Fig 15. I2C-bus protocol
After an acknowledgement, one or more command bytes follow, that define the status of each addressed PCF8562. The last command byte sent is identified by resetting its most significant bit, continuation bit C, (see Figure 16). The command bytes are also acknowledged by all addressed PCF8562s on the bus.
MSB C REST OF OPCODE
LSB
msa833
Fig 16. Format of command byte
After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated.
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An acknowledgement after each byte is asserted only by the PCF8562s that are addressed via address lines A0, A1 and A2. After the last display byte, the I2C-bus master asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus access.
7.17 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The commands available to the PCF8562 are defined in Table 7.
Table 7. Command Bit mode-set load-data-pointer device-select bank-select blink-select
[1] Not used.
Definition of PCF8562 commands Operation Code 7 C C C C C 6 1 0 1 1 1 5 0 0 1 1 1 4
[1]
Reference 3 E P3 0 1 0 2 B P2 A2 0 A 1 M1 P1 A1 I BF1 0 M0 P0 A0 O BF0 Table 9 Table 10 Table 11 Table 12 Table 13
P4 0 1 1
All available commands carry a continuation bit C in their most significant bit position as shown in Figure 16. When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is reset, it indicates that the command byte is the last in the transfer. Further bytes will be regarded as display data (see Table 8).
Table 8. Bit 7 C bit description Symbol C 0 1 Value Description continue bit last control byte in the transfer; next byte will be regarded as display data control bytes continue; next byte will be a command too
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Mode-set command bits description Symbol C E 0 1 Value 0, 1 10 Description see Table 8 fixed value unused display status disabled (blank)[1] enabled LCD bias configuration 0 1
1 3 1 2
Table 9. Bit 7 6, 5 4 3
2
B
bias bias
1 to 0
M[1:0] 01 10 11 00
LCD drive mode selection static; BP0 1:2 multiplex; BP0, BP1 1:3 multiplex; BP0, BP1, BP2 1:4 multiplex; BP0, BP1, BP2, BP3
[1]
The possibility to disable the display allows implementation of blinking under external control.
Table 10. Bit 7 6, 5 4 to 0
Load-data-pointer command bits description Symbol C P[4:0] Value 0, 1 00 00000 to 11111 Description see Table 8 fixed value 5 bit binary value, 0 to 31; transferred to the data pointer to define one of 32 display RAM addresses
Table 11. Bit 7 6 to 3 2 to 0
Device-select command bits description Symbol C A[2:0] Value 0, 1 1100 000 to 111 Description see Table 8 fixed value 3 bit binary value, 0 to 7; transferred to the subaddress counter to define one of eight hardware subaddresses
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Bank-select command bits description Symbol C I 0 1 Value 0, 1 11110 Description Static 1:2 multiplex[1] see Table 8 fixed value input bank selection; storage of arriving display data RAM bit 0 RAM bit 2 RAM bit 0 RAM bit 2 RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3
Table 12. Bit 7 6 to 2 1
0
O 0 1
output bank selection; retrieval of LCD display data
[1]
The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
Table 13. Bit 7 6 to 3 2
Blink-select command bits description Symbol C A 0 1 Value 0, 1 1110 Description see Table 8 fixed value blink mode selection normal blinking[1] alternate RAM bank blinking[2] blink frequency selection 00 01 10 11 off 1 2 3
1 to 0
BF[1:0]
[1] [2]
Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. Alternating RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
7.18 Display controller
The display controller executes the commands identified by the command decoder. It contains the device's status registers and coordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order.
7.19 Multiple chip operation
For large display configurations or for more segments (> 128 elements) to drive please refer to the PCF8576D device. The contact resistance between the SYNC input/output on each cascaded device must be controlled. If the resistance is too high, the device will not be able to synchronize properly; this is particularly applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 14.
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SYNC contact resistance Maximum contact resistance 6000 2200 1200 700
Table 14. 2 3 to 5 6 to 10 10 to 16
Number of devices
8. Internal circuitry
VDD VDD
SA0
VSS VDD
VSS
CLK SCL VSS VDD VSS OSC
VSS VDD SDA
SYNC
VSS VDD
VSS
A0, A1, A2
VSS VLCD BP0, BP1, BP2, BP3 VSS VLCD VLCD
S0 to S31 VSS
001aac269
VSS
Fig 17. Device protection circuits
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9. Limiting values
CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 15. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD VLCD VI supply voltage LCD supply voltage input voltage on each of the pins CLK, SDA, SCL, SYNC, SA0, OSC, A0 to A2 on each of the pins S0 to S31, BP0 to BP3 Conditions Min -0.5 -0.5 -0.5 Max 6.5 +7.5 +6.5 Unit V V V
VO II IO IDD IDD(LCD) ISS Ptot Po Vesd
output voltage input current output current supply current LCD supply current ground supply current total power dissipation output power electrostatic discharge voltage
-0.5 -10 -10 -50 -50 -50 -
+7.5 +10 +10 +50 +50 +50 400 100 2000 200 2000 100 +150
V mA mA mA mA mA mW mW V V V mA C
HBM MM CDM
[1] [2] [3] [4] [5]
-65
Ilu Tstg
[1] [2] [3] [4] [5]
latch-up current storage temperature
Pass level; Human Body Model (HBM) according to JESD22-A114. Pass level; Machine Model (MM), according to JESD22-A115.
Pass level; Charged-Device Model (CDM), according to JESD22-C101. Pass level; latch-up testing, according to JESD78. According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be stored at a temperature of +5 C to +45 C and a humidity of 25 % to 75 %.
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10. Static characteristics
Table 16. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD VLCD IDD IDD(LCD) Logic VP(POR) VIL power-on reset supply voltage LOW-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, SCL, SDA on pins CLK, SYNC, OSC, A0 to A2, SA0, SCL, SDA VOL = 0.4 V; VDD = 5 V on pins CLK and SYNC on pin SDA IOH(CLK) IL HIGH-level output current on pin CLK leakage current VOH = 4.6 V; VDD = 5 V VI = VDD or VSS; on pins CLK, SCL, SDA, A0 to A2 and SA0 VI = VDD
[5] [3][4]
Parameter supply voltage LCD supply voltage supply current LCD supply current
Conditions
Min 1.8
[1]
Typ 8 24 1.3 -
Max 5.5 6.5 20 60 1.6 0.3VDD
Unit V V A A V V
2.5 1.0 VSS
fclk = 1536 Hz fclk = 1536 Hz
[2] [2]
VIH
HIGH-level input voltage
0.7VDD
-
VDD
V
IOL
LOW-level output current
1 3 -1 -1
-
+1
mA mA mA A
IL(OSC) CI VO RO
leakage current on pin OSC input capacitance output voltage variation output resistance
-1 -100
[6]
-
+1 7 +100
A pF mV
LCD outputs on pins BP0 to BP3 and S0 to S31 VLCD = 5 V on pins BP0 to BP3 on pins S0 to S31
[1] [2] [3] [4] [5] [6] VLCD > 3 V for 13 bias. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 15 (see Figure 17 too). Propagation delay of driver between clock (CLK) and LCD driving signals. Periodically sampled, not 100 % tested. Outputs measured one at a time.
-
1.5 6.0
-
k k
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11. Dynamic characteristics
Table 17. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Clock fclk(int) fclk(ext) tclk(H) tclk(L) internal clock frequency external clock frequency HIGH-level clock time LOW-level clock time
[1]
Parameter
Conditions
Min 1440 960 60 60 1
Typ 1850 30 -
Max 2640 2640 30
Unit Hz Hz s s ns s s
Synchronization tPD(SYNC_N) SYNC propagation delay tSYNC_NL tPD(drv) I2C-bus[3] Pin SCL fSCL tLOW tHIGH Pin SDA tSU;DAT tHD;DAT tBUF tSU;STO tHD;STA tSU;STA tr tf Cb tw(spike)
[1] [2] [3]
SYNC LOW time driver propagation delay VLCD = 5 V
[2]
-
SCL clock frequency LOW period of the SCL clock HIGH period of the SCL clock data set-up time data hold time bus free time between a STOP and START condition set-up time for STOP condition hold time (repeated) START condition set-up time for a repeated START condition rise time of both SDA and SCL signals fSCL = 400 kHz fSCL < 125 kHz fall time of both SDA and SCL signals capacitive load for each bus line spike pulse width on the I2C-bus
1.3 0.6 100 0 1.3 0.6 0.6 0.6 -
-
400 0.3 1.0 0.3 400 50
kHz s s ns ns s s s s s s s pF ns
Pins SCL and SDA
Typical output duty factor: 50 % measured at the CLK output pin. Not tested in production. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD.
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1/fCLK tCLKH tCLKL 0.7VDD CLK 0.3VDD
0.7VDD SYNC 0.3VDD tPD(SYNC) tSYNCL BP0 to BP3, and S0 to S31 0.5 V (VDD = 5 V) 0.5 V tPD(LCD)
001aac268
tPD(SYNC)
Fig 18. Driver timing waveforms
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA tSU;STO
mga728
Fig 19. I2C-bus timing waveforms
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12. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
D
E
A X
c y HE vMA
Z
48
25
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp
24
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 20. Package outline SOT362-1 (TSSOP48)
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13. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards.
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
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14.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 14.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 21) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 18 and 19
Table 18. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 19. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 21.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 21. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
15. Abbreviations
Table 20. Acronym CMOS CDM HBM ITO LCD LSB MM MSB MSL PCB RAM RMS SCL SDA SMD Abbreviations Description Complementary Metal Oxide Semiconductor Charged-Device Model Human Body Model Indium Tin Oxide Liquid Crystal Display Least Significant Bit Machine Model Most Significant Bit Moisture Sensitivity Level Printed Circuit Board Random Access Memory Root Mean Square Serial Clock Line Serial Data Line Surface Mount Device
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16. Revision history
Table 21. Revision history Release date 20090318 Data sheet status Product data sheet Product data sheet Change notice Supersedes PCF8562_3 PCF8562_2 Document ID PCF8562_4 Modifications: PCF8562_3 Modifications:
* * * *
The typical value of the frame frequency has been corrected (see Table 17) The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added AEC-Q100 qualification Product data sheet Product data sheet PCF8562_1 -
20081202
PCF8562_2 PCF8562_1
20070122 20050801
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17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Universal LCD driver for low multiplex rates
19. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.16.1 7.16.2 7.16.3 7.16.4 7.16.5 7.16.6 7.16.7 7.17 7.18 7.19 8 9 10 11 12 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 LCD bias generator. . . . . . . . . . . . . . . . . . . . . . 6 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 6 LCD drive mode waveforms . . . . . . . . . . . . . . . 9 Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9 1:2 Multiplex drive mode . . . . . . . . . . . . . . . . . 10 1:3 Multiplex drive mode . . . . . . . . . . . . . . . . . 12 1:4 Multiplex drive mode . . . . . . . . . . . . . . . . . 13 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 14 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Display register . . . . . . . . . . . . . . . . . . . . . . . . 14 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 14 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Subaddress counter . . . . . . . . . . . . . . . . . . . . 17 Output bank selector. . . . . . . . . . . . . . . . . . . . 17 Input bank selector . . . . . . . . . . . . . . . . . . . . . 18 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Characteristics of the I2C-bus . . . . . . . . . . . . . 19 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 START and STOP conditions . . . . . . . . . . . . . 19 System configuration . . . . . . . . . . . . . . . . . . . 19 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 20 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21 Command decoder . . . . . . . . . . . . . . . . . . . . . 22 Display controller . . . . . . . . . . . . . . . . . . . . . . 24 Multiple chip operation . . . . . . . . . . . . . . . . . . 24 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 25 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 Static characteristics. . . . . . . . . . . . . . . . . . . . 27 Dynamic characteristics . . . . . . . . . . . . . . . . . 28 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 30 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 Handling information . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 31 31 31 32 32 33 34 35 35 35 35 35 35 36
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 March 2009 Document identifier: PCF8562_4

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